// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_sdi_axim_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_SDI_AXIM_REG_REG_OFFSET_H__
#define __HIPCIEC_AP_SDI_AXIM_REG_REG_OFFSET_H__

/* HIPCIEC_AP_SDI_AXIM_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE                       (0x13000)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_AP_SDI_AXIM_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_SDI_SMMU_BYPASS_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x0)   /* SMMU BYPASS CONTROL  of DMA/iEP request */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_SDI_ODR_MODE_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x4)   /* Ordering Mode CONTROL */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_SDI_ETH_CFG_ATTR_REG             (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x10)  /* the cache/snp attribute control of ETH config reqeust */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_DMA_ATTR_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x20)  /* the memory attribute control of DMA */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_DMA_MEM_DAW_0_H_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x28)  /* high 16bit of DMA DAW 0 upper address */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_DMA_MEM_DAW_0_L_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2C)  /* low 32bit of DMA DAW 0 upper address */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_DMA_MEM_DAW_1_H_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x30)  /* high 16bit of DMA DAW 1 upper address */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_DMA_MEM_DAW_1_L_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x34)  /* low 32bit of DMA DAW 1 upper address */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_DMA_MEM_DAW_2_H_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x38)  /* high 16bit of DMA DAW 2 upper address */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_DMA_MEM_DAW_2_L_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x3C)  /* low 32bit of DMA DAW 2 upper address */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_ATTR_0_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x40)  /* the cache/snp attribute control of MCTP operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_ATTR_1_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x44)  /* the cache/snp attribute control of MCTP operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_ATTR_2_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x48)  /* the cache/snp attribute control of MCTP operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_MEM_DAW_0_LL_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x50)  /* the MCTP cache/snp configuration DAW 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_MEM_DAW_0_LH_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x54)  /* the MCTP cache/snp configuration DAW 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_MEM_DAW_0_HL_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x58)  /* the MCTP cache/snp configuration DAW 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_MEM_DAW_0_HH_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x5C)  /* the MCTP cache/snp configuration DAW 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_MEM_DAW_1_LL_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x60)  /* the MCTP cache/snp configuration DAW 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_MEM_DAW_1_LH_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x64)  /* the MCTP cache/snp configuration DAW 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_MEM_DAW_1_HL_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x68)  /* the MCTP cache/snp configuration DAW 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_CTRL_MCTP_MEM_DAW_1_HH_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x6C)  /* the MCTP cache/snp configuration DAW 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_INT_SRC_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x80)  /* sdi_axim int source */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_INT_MASK_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x84)  /* sdi_axim int mask */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_INT_STS_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x8C)  /* sdi_axim int state */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_MEM_ECC_INJECT_REG                (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x90)  /* ECC error inject control */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_SBM_ECC_STATE_REG             (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x100) /* ECC counter and address of NPQ SBM */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_SBM_ECC_STATE_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x104) /* ECC counter and address of PQ_SBM */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_SBM_STATE_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x108) /* State of NPQ_SBM */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_QUEUE_DISP_STATE_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x10C) /* State of QUEUE_DISP */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_PORT_STATE_REG                (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x110) /* State of PQ/NPQ port */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_SEND_RO_REG                    (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x114) /* State of PQ_SEND */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_SBM_RO_0_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x118) /* State of PQ_SBM_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_SBM_RO_1_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x11C) /* State of PQ_SBM_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_TBL_RO_0_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x120) /* State of NPQ_TBL_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_TBL_RO_1_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x124) /* State of NPQ_TBL_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_TBL_RO_2_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x128) /* State of NPQ_TBL_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_TBL_RO_3_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x12C) /* State of NPQ_TBL_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_TBL_RO_0_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x130) /* State of PQ_TBL_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_TBL_RO_1_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x134) /* State of PQ_TBL_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_TBL_RO_2_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x138) /* State of PQ_TBL_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_TBL_RO_3_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x13C) /* State of PQ_TBL_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_TBL_RD_REQ_REG                (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x140) /* NPQ_TBL read request */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_NPQ_TBL_RD_RO_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x144) /* NPQ_TBL read ro */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_TBL_RD_REQ_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x148) /* PQ_TBL read request */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_PQ_TBL_RD_RO_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x14C) /* PQ_TBL read ro */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_HDR_BUF_RD_REQ_REG                (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x150) /* hdr_buf read reqeust */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_HDR_BUF_RD_RO_0_REG               (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x154) /* hdr_buf read ro 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_HDR_BUF_RD_RO_1_REG               (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x158) /* hdr_buf read ro 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_HDR_BUF_RD_RO_2_REG               (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x15C) /* hdr_buf read ro 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_DFX_TLB_ABORT_CNT_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x160) /* tlb_abort counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_GLOBAL_CTRL_REG              (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x200) /* AXIM global control */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_MAX_TRANS_CTRL_REG           (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x204) /* AXIM max outstanding number control */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_QOS_CTRL_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x208) /* AXIM qos control */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_ARUSER_MODE_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x220) /* AXIM aruser control. */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_ARUSER_SET_0_REG             (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x224) /* AXIM aruser vaule set, index 0. */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_ARUSER_SET_1_REG             (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x228) /* AXIM aruser vaule set, index 1. */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_ARUSER_SET_2_REG             (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x22C) /* AXIM aruser value set, index 2. */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_AWUSER_MODE_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x230) /* AXIM awuser control. */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_AWUSER_SET_0_REG             (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x234) /* AXIM awuser vaule set, index 0. */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_AWUSER_SET_1_REG             (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x238) /* AXIM awuser vaule set, index 1. */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_AWUSER_SET_2_REG             (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x23C) /* AXIM awuser value set, index 2. */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_MAX_TRANS_REG            (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x280) /* AXIM max used outstanding number */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_DAT_STS_REG           (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x284) /* AXIM data channel state */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_AXI_RESP_ERR_STS_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x288) /* AXI response error state */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_AXI_GEN_REQ_REG          (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x28C) /* AXI Request state */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RD_TXID_STS_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x290) /* AXIM read transacion id state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RD_TXID_STS_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x294) /* AXIM read transacion id state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RD_TXID_STS_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x298) /* AXIM read transacion id state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RD_TXID_STS_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x29C) /* AXIM read transacion id state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_TXID_STS_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2A0) /* AXIM write transacion id state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_TXID_STS_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2A4) /* AXIM write transacion id state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_TXID_STS_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2A8) /* AXIM write transacion id state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_TXID_STS_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2AC) /* AXIM write transacion id state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RRESP_CONFLICT_STS_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2B0) /* AXIM RRESP conflict state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RRESP_CONFLICT_STS_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2B4) /* AXIM RRESP conflict state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RRESP_CONFLICT_STS_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2B8) /* AXIM RRESP conflict state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RRESP_CONFLICT_STS_3_REG (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2BC) /* AXIM RRESP conflict state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_BRESP_CONFLICT_STS_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2C0) /* AXIM BRESP conflict state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_BRESP_CONFLICT_STS_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2C4) /* AXIM BRESP conflict state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_BRESP_CONFLICT_STS_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2C8) /* AXIM BRESP conflict state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_BRESP_CONFLICT_STS_3_REG (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2CC) /* AXIM BRESP conflict state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_MEM_RD_LATENCY_REG       (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2D0) /* AXIM read latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_P2P_RD_LATENCY_REG       (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2D4) /* AXIM read latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_MEM_WR_LATENCY_REG       (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2D8) /* AXIM write latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_P2P_WR_LATENCY_REG       (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2DC) /* AXIM write latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RD_TLP_PAYLOAD_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2E0) /* Input NP TLP payload 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RD_TLP_PAYLOAD_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2E4) /* Input NP TLP payload 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RD_TLP_PAYLOAD_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2E8) /* Input NP TLP payload 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_RD_TLP_PAYLOAD_3_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2EC) /* Input NP TLP payload 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_TLP_PAYLOAD_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2F0) /* Input P TLP payload 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_TLP_PAYLOAD_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2F4) /* Input P TLP payload 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_TLP_PAYLOAD_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2F8) /* Input P TLP payload 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_SDI_AXIM_DFX_WR_TLP_PAYLOAD_3_REG     (HiPCIECTRL40V200_HIPCIEC_AP_SDI_AXIM_REG_BASE + 0x2FC) /* Input P TLP payload 3 */

#endif // __HIPCIEC_AP_SDI_AXIM_REG_REG_OFFSET_H__
